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DAC8043
Rev. E | Page 10 of 16
DIGITAL SECTION
The digital inputs of the DAC8043 (SRI, LD, and CLK) are TTL
compatible. The input voltage levels affect the amount of current
drawn from the supply; peak supply current occurs as the digital
input (VIN) passes through the transition region (see Figure 6).
Maintaining the digital input voltage levels as close as possible
to the VDD and GND supplies minimizes supply current
consumption.
The digital inputs of the DAC8043 have been designed with
ESD resistance incorporated through careful layout and the
inclusion of input protection circuitry. Figure 11 shows the input
protection diodes and series resistor; this input structure is
duplicated on each digital input. High voltage static charges
applied to the inputs are shunted to the supply and ground rails
through forward biased diodes. These protection diodes were
designed to clamp the inputs to well below dangerous levels
during static discharge conditions.
GENERAL CIRCUIT INFORMATION
The DAC8043 is a 12-bit multiplying digital-to-analog
converter (DAC) with a very low temperature coefficient.
It contains an R-2R resistor ladder network, data input,
control logic, and two data registers.
00271-
0
1
TL/TTL/CMOS
INPUTS
VDD
Figure 11. Digital Input Protection
The digital circuitry forms an interface in which serial data
can be loaded under microprocessor control into a 12-bit shift
register and then transferred, in parallel, to the 12-bit DAC
register.
A simplified circuit of the DAC8043 is shown in Figure 13,
which has an inverted R-2R ladder network consisting of silicon-
chrome, highly stable (50 ppm/°C) thin-film resistors, and
twelve pairs of NMOS current-steering switches.
These switches steer binarily weighted currents into either IOUT
or GND; this yields a constant current in each ladder leg, regardless
of digital input code. This constant current results in a constant
input resistance at VREF equal to R. The VREF input may be driven by
any reference voltage or current, ac or dc, that is within the limits
stated in the Absolute Maximum Ratings section.
The twelve output current-steering NMOS FET switches are in
series with each R-2R resistor; they can introduce bit errors if all
are of the same RON resistance value. They were designed so that
the switch on resistance is binarily scaled so that the voltage drop
across each switch remains constant. If, for example, Switch S1 of
Figure 13 was designed with an on resistance of 10 , Switch S2 for
20 , and so on, a constant 5 mV drop would be maintained across
each switch.
BIT 12 LSB
BIT 1 MSB1
BIT 11
SRI
CLK INPUT
1DATA LOADED MSB FIRST.
BIT 2
LD
tDS
tDH
tASB
tLD
tCH
tCL
1
2
11
LOAD SERIAL DATA
INTO INPUT REGISTER
LOAD INPUT REGISTER’S
DATA INTO DAC REGISTER
00271-
012
Figure 12. Write Cycle Timing Diagram
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